Complementary NMOS and PMOS pair gives logic with near-zero static power.
PMOS pulls the output up and NMOS pulls it down, so only one conducts at a time, with essentially zero static current. Power is dynamic: P=αCV²f. Noise margins are large and the design scales well, making CMOS the base of processors and memories.
A modern CPU has billions of CMOS gates.
CMOS logic is the technology of almost all digital chips because it draws very little static power, which allows billions of transistors on one die.
Complementary NMOS and PMOS pair gives logic with near-zero static power.
CMOS logic is the technology of almost all digital chips because it draws very little static power, which allows billions of transistors on one die.
One device pulls the output high while the other pulls it low, so one is always off in steady state, which removes static current.
Each switching event charges and discharges the load capacitance, so dynamic power grows with switching frequency and voltage squared.
Typical applications include building a NAND gate in a microcontroller, explaining why a static CMOS chip draws little power when idle and choosing a low-power logic family for a battery device.
Study "MOSFET regions of operation" first (topic 14 of 104 in Electronics & Embedded). It covers the groundwork this topic builds on.
Rail-to-rail output. Propagation delay. Latch-up risk.
A modern CPU has billions of CMOS gates.
The next topic is "Small-signal models", which builds directly on this one.
It is classed as Beginner in Electronics & Embedded (topic 15 of 104). It is an entry-level topic. It relies only on basic school mathematics and the ideas introduced earlier in this discipline.
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