SR, D, JK and T devices store one bit and change on clock edges.
SR latch, D flip-flop (captures D at the clock edge), JK (toggles when J=K=1), T (toggle). Edge-triggered flip-flops avoid race conditions. Characteristic equations and excitation tables support design. Asynchronous set/reset override the clock.
Dividing a clock by 2 uses a T flip-flop.
Flip-flops store a bit of state and change only on clock edges, which makes them the heart of registers, counters and state machines.
SR, D, JK and T devices store one bit and change on clock edges.
Flip-flops store a bit of state and change only on clock edges, which makes them the heart of registers, counters and state machines.
A latch is level sensitive and transparent while enabled. A flip-flop changes only on a clock edge, which makes it more predictable in synchronous designs.
It captures its input on the clock edge and holds it, which is simple, reliable and the basis of most register designs.
Typical applications include holding a button state in a register until the software reads it, building a counter that increments on each clock pulse and synchronising an asynchronous input to a clock domain.
Study "Multiplexers and decoders" first (topic 42 of 104 in Electronics & Embedded). It covers the groundwork this topic builds on.
Master-slave. Metastability when timing violated. D flip-flop most common.
Dividing a clock by 2 uses a T flip-flop.
The next topic is "Registers and counters", which builds directly on this one.
It is classed as Intermediate in Electronics & Embedded (topic 43 of 104). It is an intermediate topic. Work through the beginner topics in Electronics & Embedded first.
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