Feedback circuits that lock an oscillator to a reference frequency.
A PLL has a phase detector, loop filter and VCO with a divider in feedback, locking output to a multiple of the reference: f_out=N·f_ref. Used for clock generation, frequency synthesis, demodulation and clock recovery. Parameters: lock time, jitter, loop bandwidth.
A PLL multiplies a 25 MHz crystal to a 1 GHz CPU clock.
PLLs lock an oscillator to a reference, which generates clocks for processors, radios and synthesisers from a single crystal.
Feedback circuits that lock an oscillator to a reference frequency.
PLLs lock an oscillator to a reference, which generates clocks for processors, radios and synthesisers from a single crystal.
A phase detector, a loop filter and a voltage-controlled oscillator, with a divider in the feedback path for frequency multiplication.
It smooths the control voltage and sets the loop bandwidth, which controls how quickly the PLL locks and how much jitter it passes.
Typical applications include generating a 96 MHz system clock from an 8 MHz crystal in a microcontroller, recovering the clock from a serial data stream in a receiver and synthesising the carrier frequency of a radio transmitter.
Study "Analog-mixed-signal design" first (topic 98 of 104 in Electronics & Embedded). It covers the groundwork this topic builds on.
Charge pump. Integer-N vs fractional-N. Phase noise.
A PLL multiplies a 25 MHz crystal to a 1 GHz CPU clock.
The next topic is "SoC architectures", which builds directly on this one.
It is classed as Advanced in Electronics & Embedded (topic 99 of 104). It is an advanced topic. It assumes you are comfortable with the intermediate topics in Electronics & Embedded.
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