Data must be stable around the clock edge to be captured correctly.
Setup time: input must be stable before the clock edge; hold time: stable after it. Violations cause metastability. Clock period T≥t_clk-to-q+t_logic+t_setup+skew. Static timing analysis checks all paths. Fix with pipelining or retiming.
Crossing clock domains requires a two-flip-flop synchroniser.
Setup and hold times decide whether data is captured correctly, so timing violations are a common source of intermittent faults.
Data must be stable around the clock edge to be captured correctly.
Setup and hold times decide whether data is captured correctly, so timing violations are a common source of intermittent faults.
The minimum time the data must be stable before the active clock edge so the flip-flop captures it correctly.
When a flip-flop samples data that changes near the clock edge, its output can hover between states for a time, which is handled with synchronisers.
Typical applications include checking that a data bus meets setup time at a faster clock speed, diagnosing random errors that appear only when a clock is raised and designing the clock tree of an FPGA with tight timing margins.
Study "Finite state machines" first (topic 45 of 104 in Electronics & Embedded). It covers the groundwork this topic builds on.
Clock skew and jitter. Synchronisers for asynchronous inputs. Maximum frequency.
Crossing clock domains requires a two-flip-flop synchroniser.
The next topic is "Memory types", which builds directly on this one.
It is classed as Intermediate in Electronics & Embedded (topic 46 of 104). It is an intermediate topic. Work through the beginner topics in Electronics & Embedded first.
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