Add scan chains and test points to find manufacturing defects.
DFT adds scan chains, built-in self-test (BIST), boundary scan (JTAG) and test points so defects can be detected and diagnosed. Metrics: fault coverage, test time. On PCBs, provide access for bed-of-nails and flying-probe testing.
Scan chain converts flip-flops into a shift register for testing.
Design for testability adds features that make manufacturing faults easy to find, which reduces test cost and speeds up production.
Add scan chains and test points to find manufacturing defects.
Design for testability adds features that make manufacturing faults easy to find, which reduces test cost and speeds up production.
A chain of flip-flops connected so their states can be shifted in and out for testing, which gives access to internal logic.
They give probes a way to reach key nets on a board, which helps diagnose faults quickly during production testing.
Typical applications include adding test points to a board for fast in-circuit testing, including scan chains in an ASIC to check logic after fabrication and providing a JTAG port so a board can be tested automatically.
Study "Hardware-in-the-loop testing" first (topic 94 of 104 in Electronics & Embedded). It covers the groundwork this topic builds on.
Stuck-at faults. ATPG. Memory BIST.
Scan chain converts flip-flops into a shift register for testing.
The next topic is "Signal integrity", which builds directly on this one.
It is classed as Advanced in Electronics & Embedded (topic 95 of 104). It is an advanced topic. It assumes you are comfortable with the intermediate topics in Electronics & Embedded.
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