Voltage scaling, power gating and duty cycling extend battery life.
Dynamic power P=αCV²f, so lower voltage and frequency (DVFS), clock gating, power gating, multi-threshold cells and architectural parallelism reduce energy. Software tactics: race-to-sleep, batching I/O, event-driven design. Leakage dominates at advanced nodes.
Halving supply voltage cuts dynamic power to a quarter.
Low-power design extends battery life, and it is often more important than peak performance in portable and remote products.
Voltage scaling, power gating and duty cycling extend battery life.
Low-power design extends battery life, and it is often more important than peak performance in portable and remote products.
Reducing the supply voltage and clock frequency when full performance is not needed, which cuts dynamic power sharply because power depends on voltage squared.
Dynamic power comes from switching and rises with frequency. Static power is leakage that flows even when the logic is idle, and it grows with temperature.
Typical applications include running a wearable for weeks by duty-cycling its radio, scaling the voltage of a processor when the load is light and shutting off unused blocks with power gating in an SoC.
Study "SoC architectures" first (topic 100 of 104 in Electronics & Embedded). It covers the groundwork this topic builds on.
Energy per operation. Always-on domain. Retention registers.
Halving supply voltage cuts dynamic power to a quarter.
The next topic is "Reliability and functional safety", which builds directly on this one.
It is classed as Advanced in Electronics & Embedded (topic 101 of 104). It is an advanced topic. It assumes you are comfortable with the intermediate topics in Electronics & Embedded.
Want to practise? Open the interactive course for quick checks, quizzes, simulations and progress tracking.