RTL, synthesis, place and route, verification and tape-out.
RTL design, functional verification, synthesis, floorplan, place and route, timing and power sign-off, physical verification (DRC/LVS), tape-out, fabrication, testing. Costs and turnaround are high so verification is critical. Process nodes from 180 nm to 3 nm.
A smartphone SoC takes years from RTL to production.
The ASIC flow is how custom chips are made, and understanding it helps you plan costs, schedules and verification effort.
RTL, synthesis, place and route, verification and tape-out.
The ASIC flow is how custom chips are made, and understanding it helps you plan costs, schedules and verification effort.
Register transfer level code that describes the registers and logic between them, which is the input to synthesis.
A mistake found after fabrication requires a new mask set, which costs a great deal of money and time.
Typical applications include taking a new radio chip from RTL design to manufacture, estimating the non-recurring cost of a custom sensor chip and planning verification before tape-out to avoid expensive respins.
Study "FPGA" first (topic 53 of 104 in Electronics & Embedded). It covers the groundwork this topic builds on.
Design rules. Mask sets are expensive. Yield.
A smartphone SoC takes years from RTL to production.
The next topic is "Microprocessor vs microcontroller", which builds directly on this one.
It is classed as Intermediate in Electronics & Embedded (topic 54 of 104). It is an intermediate topic. Work through the beginner topics in Electronics & Embedded first.
Want to practise? Open the interactive course for quick checks, quizzes, simulations and progress tracking.